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On automatic-verification pattern generation for SoC with port-order fault model

Chun-Yao Wang Shing-Tung Yau Jing-Yang Jou

TBD mathscidoc:1912.43575

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21, (4), 466-479, 2019.8
Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tang and Jou, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage.
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@inproceedings{chun-yao2019on,
  title={On automatic-verification pattern generation for SoC with port-order fault model},
  author={Chun-Yao Wang, Shing-Tung Yau, and Jing-Yang Jou},
  url={http://archive.ymsc.tsinghua.edu.cn/pacm_paperurl/20191224204151087297139},
  booktitle={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  volume={21},
  number={4},
  pages={466-479},
  year={2019},
}
Chun-Yao Wang, Shing-Tung Yau, and Jing-Yang Jou. On automatic-verification pattern generation for SoC with port-order fault model. 2019. Vol. 21. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp.466-479. http://archive.ymsc.tsinghua.edu.cn/pacm_paperurl/20191224204151087297139.
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